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products and specifications discussed herein ar e subject to change by micron without notice. 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm features pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 1 ?2005 micron technology, inc. all rights reserved. ddr sdram vlp rdimm mt18vdvf12872 ? 1gb for component data sheets, refer to micron?s web site: www.micron.com features ? 184-pin, very low profile registered dual in-line memory module (vlp rdimm) ? fast data transfer rates: pc2700 or pc3200 ? 1gb (128 meg x 72) ? supports ecc error detection and correction ?v dd = v dd q = +2.5v (-40b: v dd = v dd q = +2.6v) ?v ddspd = +2.3v to +3.6v ? 2.5v i/o (sstl_2-compatible) ? internal pipelined double data rate (ddr) 2 n -prefetch architecture ? bidirectional data strobe (dqs) transmitted/ received with data?that is, source-synchronous data capture ? differential clock inputs (ck and ck#) ? multiple internal device banks for concurrent operation ? single rank ? selectable burst lengths (bl): 2, 4, or 8 ? auto precharge option ? auto refresh and self refresh modes: 7.8125s maximum average periodic refresh interval ? serial presence-det ect (spd) with eeprom ? selectable cas latency (cl) for maximum compatibility ? gold edge contacts figure 1: 184-pin vlp rdimm (mo-206) notes: 1. contact micron for industrial temperature module offerings. 2. cl = cas (read) latency; registered mode adds one clock cycle to cl. options marking ? operating temperature 1 ? commercial (0c t a +70c) none ? industrial (?40c t a +85c) i ?package ? 184-pin dimm (standard) g ? 184-pin dimm (pb-free) y ? memory clock, speed, cas latency 2 ? 5.0ns (200 mhz), 400 mt/s, cl = 3 -40b ? 6.0ns (166 mhz), 333 mt/s, cl = 2.5 -335 p c b hei g ht: 18.29mm (0.72in) notes: 1. the values of t rcd and t rp for -335 modules show 18ns to a lign with industry specifications; actual ddr sdram device specifications are 15ns. table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) notes cl = 3 cl = 2.5 cl = 2 -40b pc3200 400 333 266 15 15 55 -335 pc2700 ? 333 266 18 18 60 1
pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 2 ?2005 micron technology, inc. all rights reserved 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm features notes: 1. data sheets for the base device can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown) that desi gnates component and pcb revisions. consult factor y for current revision codes. example: mt18vdvf12872y-335f1 . table 2: addressing parameter 1gb refresh count 8k row address 8k (a0?a12) device bank address 4 (ba0, ba1) device configuration 512mb (128 meg x 4) column address 4k (a0?a9, a11, a12) module rank address 1 (s0#) table 3: part numbers and timing parameters ? 1gb modules base device: mt46v128m4, 1 512mb ddr sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt18vdvf12872g-40b__ 1gb 128 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18vdvf12872y-40b__ 1gb 128 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18vdvf12872g-335__ 1gb 128 meg x 72 2.7 gb/s 6.0ns/333 mt/s 3-3-3 mt18vdvf12872y-335__ 1gb 128 meg x 72 2.7 gb/s 6.0ns/333 mt/s 3-3-3
pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 3 ?2005 micron technology, inc. all rights reserved 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm pin assignments and descriptions pin assignments and descriptions table 4: pin assignments 184-pin vlp rdimm front 184-pin vlp rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref 24 dq17 47 dqs8 70 v dd 93 v ss 116 v ss 139 v ss 162 dq47 2 dq0 25 dqs2 48 a0 71 nc 94 dq4 117 dq21 140 dqs17 163 nc 3v ss 26 v ss 49 cb2 72 dq48 95 dq5 118 a11 141 a10 164 v dd q 4 dq1 27 a9 50 v ss 73 dq49 96 v dd q 119 dqs11 142 cb6 165 dq52 5dqs028dq1851 cb3 74 v ss 97 dqs9 120 v dd 143 v dd q 166 dq53 6 dq2 29 a7 52 ba1 75 nc 98 dq6 121 dq22 144 cb7 167 nc 7v dd 30 v dd q 53 dq32 76 nc 99 dq7 122 a8 145 v ss 168 v dd 8 dq3 31 dq19 54 v dd q77v dd q100v ss 123 dq23 146 dq36 169 dqs15 9 nc 32 a5 55dq3378dqs6 101 nc 124 v ss 147 dq37 170 dq54 10 reset# 33 dq24 56 dqs4 79 dq50 102 nc 125 a6 148 v dd 171 dq55 11 v ss 34 v ss 57 dq34 80 dq51 103 nc 126 dq28 149 dqs13 172 v dd q 12 dq8 35 dq25 58 v ss 81 v ss 104 v dd q 127 dq29 150 dq38 173 nc 13 dq9 36 dqs3 59 ba0 82 nc 105 dq12 128 v dd q 151 dq39 174 dq60 14 dqs1 37 a4 60 dq35 83 dq56 106 dq13 129 dqs12 152 v ss 175 dq61 15 v dd q38 v dd 61 dq40 84 dq57 107 dqs10 130 a3 153 dq44 176 v ss 16 nc 39 dq26 62 v dd q85 v dd 108 v dd 131 dq30 154 ras# 177 dqs16 17 nc 40 dq27 63 we# 86 dqs7 109 dq14 132 v ss 155 dq45 178 dq62 18 v ss 41 a2 64 dq41 87 dq58 110 dq15 133 dq31 156 v dd q 179 dq63 19 dq10 42 v ss 65 cas# 88 dq59 111 nc 134 cb4 157 s0# 180 v dd q 20 dq11 43 a1 66 v ss 89 v ss 112 v dd q 135 cb5 158 nc 181 sa0 21 cke0 44 cb0 67 dqs5 90 nc 113 nc 136 v dd q 159 dqs14 182 sa1 22 v dd q 45 cb1 68 dq42 91 sda 114 dq20 137 ck0 160 v ss 183 sa2 23 dq16 46 v dd 69 dq43 92 scl 115 a12 138 ck0# 161 dq46 184 v ddspd
pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 4 ?2005 micron technology, inc. all rights reserved 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm pin assignments and descriptions table 5: pin descriptions symbol type description a0?a12 input address inputs: provide the row address fo r active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory a rray in the respective device bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, devi ce bank selected by ba0, ba1) or all device banks (a10 high). the address inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mode register) is load ed during the load mode register command. ba0, ba1 input bank address: ba0 and ba1 define the device bank to which an active, read, write, or precharge command is being applied. ck0, ck0# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. output data (dq and dqs) is referenced to the crossings of ck and ck#. cke0 input clock enable: cke (registered high) activa tes and cke (registered low) deactivates the internal clock, in put buffers, and output drivers. ras#, cas#, we# input command inputs: ras#, cas#, and we# (alo ng with s#) define the command being entered. reset# input reset: asynchronously forces all registered outputs low when reset# is low. this signal can be used during power-up to ensure that cke is low and dq are high-z. s0# input chip selects: s# enables (registered low) and disables (registered high) the command decoder. sa0?sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. scl input serial clock for presence-detect: scl is used to synchronize the presence- detect data transfer to and from the module. cb0?cb7 i/o check bits. dq0?dq63 i/o data input/output: data bus. dqs0?dqs17 i/o data strobe: output with read data, input with write data. dqs is edge- aligned with read data, ce nter-aligned with write data. used to capture data. sda i/o serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. v dd /v dd q supply power supply: +2.5v 0.2v (-40b: +2.6v 0.1v). v ddspd supply serial eeprom positive power supply: +2.3v to +3.6v. v ref supply sstl_2 reference voltage (v dd /2). v ss supply ground. nc ? no connect: these pins are not connected on the module.
pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 5 ?2005 micron technology, inc. all rights reserved 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm functional block diagram functional block diagram figure 2: functional block diagram u1 dq dq dq dq dq0 dq1 dq2 dq3 dqs cs# dm u22 dq dq dq dq dq60 dq61 dq62 dq63 dqs cs# dm u2 dq dq dq dq dq8 dq9 dq10 dq11 dqs cs# dm u21 dq dq dq dq dq52 dq53 dq54 dq55 dqs cs# dm u3 dq dq dq dq dq16 dq17 dq18 dq19 dqs cs# dm u20 dq dq dq dq dq44 dq45 dq46 dq47 dqs cs# dm u4 dq dq dq dq dq24 dq25 dq26 dq27 dqs cs# dm u19 dq dq dq dq dq36 dq37 dq38 dq39 dqs cs# dm u5 dq dq dq dq cb0 cb1 cb2 cb3 dqs cs# dm u18 dq dq dq dq cb4 cb5 cb6 cb7 dqs cs# dm u8 dq dq dq dq dq32 dq33 dq34 dq35 dqs cs# dm u15 dq dq dq dq dq28 dq29 dq30 dq31 dqs cs# dm u9 dq dq dq dq dq40 dq41 dq42 dq43 dqs cs# dm u14 dq dq dq dq dq20 dq21 dq22 dq23 dqs cs# dm u10 dq dq dq dq dq48 dq49 dq50 dq51 dqs cs# dm u13 dq dq dq dq dq12 dq13 dq14 dq15 dqs cs# dm u11 dq dq dq dq dq56 dq57 dq58 dq59 dqs cs# dm u12 dq dq dq dq dq4 dq5 dq6 dq7 pll ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 register x 2 ck0 ck0# dqs cs# dm dqs0 a0 sa0 spd eeprom sda a1 sa1 a2 sa2 ras# cas# cke0 we# a0?a12 ba0, ba1 s0#?s2# rras#: ddr sdram rcas#: ddr sdram rcke0: ddr sdram rwe#: ddr sdram ra0?ra12: ddr sdram rba0, rba1: ddr sdram rs0#: ddr sdram r e g i s t e r s wp scl dqs1 dqs2 dqs3 dqs8 dqs4 dqs6 dqs7 dqs5 dqs9 dqs10 dqs11 dqs12 dqs17 dqs13 dqs14 dqs15 dqs16 rs0# v ss u7 u16 u6, u17 v dd v ddspd v dd /v dd q v ref v ss spd eeprom ddr sdram ddr sdram ddr sdram vss reset#
pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 6 ?2005 micron technology, inc. all rights reserved 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm general description general description mt18vdvf12872 is a high-speed, cmos, dyna mic random access 1gb memory module organized in a x72 configuration. this mo dule uses a ddr sdram device with four internal banks. ddr sdram modules use a double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially a 2 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for ddr sdram modu les effectively consists of a single 2 n -bit-wide, one-clock-cycle data transfer at the internal dram core and two corre- sponding n -bit-wide, one-half-clock-cycle da ta transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. ddr sdram modules operate from differential clock inputs (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. register and pll operation these ddr sdram modules operate in regi stered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the ddr sdram devices on the following rising clock edge (data access is delayed by one clock cycle). a phase-lock loop (pll) on the module receives and redrives the differential clock signals (ck, ck#) to the ddr sdram devices. the register(s) and pll reduce address, command, control, and clock signal loading by isolating dram from the system controller. pll clock timing is defined by jedec specifications and ensured by use of the jedec clock reference board. registered mode will add one clock cycle to cl. serial presence-d etect operation ddr sdram modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bi t eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes are programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eepr om device (dimm) occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (dat a) signals, together with sa (2:0), which provide eight unique dimm/eeprom addresse s. write protect (wp) is tied to v ss on the module, permanently disabling hardware write protect.
pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 7 ?2005 micron technology, inc. all rights reserved 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm electrical specifications electrical specifications stresses greater than those listed in ta ble 6 may cause perman ent damage to the module. this is a stress rating only, and func tional operation of the module at these or any other conditions outside those indicated on the device data sheet is not implied. exposure to absolute maximum rating cond itions for extended periods may adversely affect reliability. notes: 1. for further information, refer to technical note tn-00-08: ?thermal applications ,? available on micron?s web site. input capacitance micron encourages designers to simulate the performance of the module to achieve optimum values. simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. jedec modules are currently designed using simulations to close timing budgets. component ac timing an d operating conditions recommended ac operating conditions are given in the ddr component data sheets. component specifications are available on micron?s web site. module speed grades correlate with component speed grades, as shown in table 7. table 6: absolute maximum ratings symbol parameter min max units v dd /v dd qv dd /v dd q supply voltage relative to v ss ?1.0 +3.6 v v in , v out voltage on any pin relative to v ss ?0.5 +3.2 v i i input leakage curren t; any input 0v v in v dd ; v ref input 0v v in 1.35v (all other pins not under test = 0v) address inputs, ras#, cas#, we#, ba, s#, cke ?5 +5 a ck, ck0 ?10 +10 i oz output leakage current; 0v v out v dd q; dq are disabled dq, dqs ?5 +5 a t a dram ambient operating temperature 1 commercial 0 +70 c industrial ?40 +85 c table 7: module and component speed grades module speed grade component speed grade -40b -5b -335 -6
pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 8 ?2005 micron technology, inc. all rights reserved 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm electrical specifications i dd specifications ta bl e 8 : i dd specifications an d conditions ? 1gb values are shown for the mt46v128m4 ddr sdram only and are computed from va lues specified in the 512mb (128 meg x 4) component data sheet parameter/condition symbol -40b -335 units operating one bank active-precharge current: t rc = t rc (min); t ck = t ck (min); dq and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 2,790 2,340 ma operating one bank active-read-precharge current: bl = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 3,330 2,880 ma precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = low i dd 2p 90 90 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in =v ref for dq and dqs i dd 2f 990 810 ma active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 810 630 ma active standby current: cs# = high; cke = high; one device bank active; t rc = t ras (max); t ck = t ck (min); dq and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 1,080 900 ma operating burst read current: bl = 2; continuous burst reads; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out =0ma i dd 4r 3,420 2,970 ma operating burst write current: bl = 2; continuous burst writes; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq and dqs inputs changing twice per clock cycle i dd 4w 3,510 3,150 ma auto refresh current t refc = t rfc (min) i dd 5 6,210 5,220 ma t refc = 7.8125s i dd 5a 198 180 ma self refresh current: cke 0.2v i dd 69090ma operating bank interleave read current: four device bank interleaving reads (bl = 4) with auto precharge; t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 8,100 7,290 ma
pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 9 ?2005 micron technology, inc. all rights reserved 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm register and pll specifications register and pll specifications notes: 1. timing and switching specifications for the register listed above are cr itical for proper oper- ation of the ddr sdram rdimm. these are mean t to be a subset of the parameters for the specific device used on the module. detailed information for this regi ster is available in jedec standard jesd82. table 9: register specifications sstv16859 devices or equivalent jesd82-4b parameter symbol pins condition min max units dc high-level input voltage v ih ( dc ) address, control, command sstl_25 v ref ( dc ) + 150 ? mv dc low-level input voltage v il ( dc ) address, control, command sstl_25 ? v ref ( dc ) - 150 mv ac high-level input voltage v ih ( ac ) address, control, command sstl_25 v ref ( dc ) + 310 v dd mv ac low-level input voltage v il ( ac ) address, control, command sstl_25 ? v ref ( dc ) - 310 mv output high voltage v oh parity output lvcmos v dd - 0.2 ? v output low voltage v ol parity output lvcmos ? 0.2 v input current i i all pins v i = v dd q or v ss q?5.0 +5.0a static standby i dd all pins reset# = v ss q (i o = 0) ? 100 a static operating i dd all pins reset# = v ss q; v i = v ih ( ac ) or v il ( dc ) i o = 0 ?varies by manufacturer ma dynamic operating (clock tree) i ddd n/a reset# = v dd , v i = v ih ( ac ) or v il ( ac ), i o = 0; ck and ck# switching 50 percent duty cycle ?varies by manufacturer a dynamic operating (per each input) i ddd n/a reset# = v dd , v i = v ih ( ac ) or v il ( ac ), i o = 0; ck and ck# switching 50 percent duty cycle; one data input switching at t ck/2, 50 percent duty cycle ?varies by manufacturer a input capacitance (per device, per pin) c i all inputs except reset# v i = v ref 250mv; v dd q = 1.8v 2.5 3.5 pf input capacitance (per device, per pin) c i reset# v i = v dd q or v ss q?varies by manufacturer pf
pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 10 ?2005 micron technology, inc. all rights reserved 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm register and pll specifications notes: 1. pll timing and switching specifications ar e critical for proper operation of the ddr dimm. this is a subset of parameters for the specific pll used. detailed pll in formation is available in jedec standard jesd82-1a. table 10: pll specifications cvf857 device or eq uivalent jesd82-1a parameter symbol min max units dc high-level input voltage v ih 1.7 v dd q + 0.3 v dc low-level input voltage v il ?0.3 0.7 v input voltage (limits) v in ?0.3 v dd q + 0.3 v input differential-pair cross voltage v ix (v dd q/2) - 0.2 (v dd q/2) + 0.2 v input differential voltage v id ( dc )0.36 v dd q + 0.6 v input differential voltage v id ( ac )0.70 v dd q + 0.6 v input current i i ?10 +10 a dynamic supply current i ddpd ?200a dynamic supply current i ddq ?300a dynamic supply current i add ?12ma input capacitance c in 2.0 3.5 pf table 11: pll clock driver timing requirements and switching characteristics parameter symbol min max units stabilization time t l? 100s input clock slew rate t slr(i) 1.0 4.0 v/ns ssc modulation frequency ? 30 50 khz ssc clock input frequency deviation ? 0 ?0.50 % pll loop bandwidth (?3db from unity gain) ? 2.0 ? mhz
pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 11 ?2005 micron technology, inc. all rights reserved 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm serial presence-detect serial presence-detect notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a vali d stop condition of a write sequence to the end of the eeprom intern al erase/program cycl e. during the write cycle, the eeprom bus interface circuit is disabled, sda rema ins high due to pull-up resis- tance, and the eeprom does not respond to its slave address. serial presence-detect data for the latest serial presence-detec t data, refer to micron?s spd page: www.micron.com/spd . table 12: serial presence-detect eeprom dc operating conditions parameter/condition symbol min max units supply voltage v ddspd 2.3 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il ?1 v ddspd 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = v ss or v dd i sb ?30a power supply current: scl clock frequency = 100 khz i cc ?2.0ma table 13: serial presence-detect eeprom ac operating conditions parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 ? s data-out hold time t dh 200 ? ns clock/data fall time t f ? 300 ns 2 clock/data rise time t r ? 300 ns 2 data-in hold time t hd:dat 0 ? s start condition hold time t hd:sta 0.6 ? s clock high period t high 0.6 ? s noise suppression time con stant at scl, sda inputs t i?50ns clock low period t low 1.3 ? s scl clock frequency f scl ? 400 khz data-in setup time t su:dat 100 ? ns start condition setup time t su:sta 0.6 ? s 3 stop condition setup time t su:sto 0.6 ? s write cycle time t wrc ? 10 ms 4
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of thei r respec- tive owners. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 1gb (x72, ecc, sr): 184-pin ddr vlp rdimm module dimensions pdf: 09005aef81c7380b/source: 09005aef81c7380e micron technology, inc., reserves the right to change products or specifications without notice. dvf18c_128x72.fm - rev. c 11/07 en 12 ?2005 micron technology, inc. all rights reserved. module dimensions figure 3: 184-pin ddr vlp rdimm notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is fo r reference only. refer to the jedec mo document for addi- tional design dimensions. 18.42 (0.725) 18.1 6 (0.715) front view 133.50 (5.25 6 ) 133.20 (5.244) 10.0 (0.394) typ ba c k view 1.37 (0.054) 1.17 (0.04 6 ) 4.0 (0.157) max u11 u1 u2 u3 u4 u5 u 6 u7 u8 u9 u10 u11 u1 6 u17 u12 u13 u14 u15 u18 u19 u20 u21 u22 pin 1 2.5 (0.098) d (2x) 2.31 (0.091) typ 6 .35 (0.25) typ 120. 6 5 (4.75) typ 1.27 (0.05) typ 2.21 (0.087) typ 1.02 (0.04) typ 2.0 (0.079) r (4x) 0.9 (0.035) r pin 92 6 4.77 (2.55) typ 49.53 (1.95) typ pin 184 pin 93 1.0 (0.039) typ 73.28 (2.88) typ 3.8 (0.15) typ
1gb ddr sdram: mt18vdvf12872y-40b illustration only. see data sh eet for product specifications. micron registered dimms isolate the command, address, and clock signals, which reduces system loading and allows a greater numb er of modules on a given system. rdimms also in clude ecc error handling and correction, incr easing data reliability. this module's ve ry low p rofile?a height of 18.29mm?improves airflow and saves board space. z z z z z z home products dram modules vlp rdimm vlp rdimm parts catalog mt18vdvf12872y-40b z z z z orde r tech notes documentation sim models page 1 of 2 mt18vdvf12872y-40b 19-nov-2010 http://www.micron.com//products/pro ductdetails.html?product=products/dram _ modules/vlp _ rdimm//mt18vdvf12872y-4 ...
MT18VDVF12872Y-40BF1 production orders are bei ng taken, parts are shipping. contact a sales representative additional info view spd data please note: distributor inventory is an estimate and may not reflect actual available memory. some links on this page will take you from the micron we b site. micron does not control the content on these web sites. ?2010 micron technolo gy , inc. all ri g hts reserve d orderable part part status buy online MT18VDVF12872Y-40BF1 production contact rep mt18vdvf12872y- 40bd4 obsolete contact rep z z privac y polic y terms of use z z z z site map contact us crucial.com lexar.com page 2 of 2 mt18vdvf12872y-40b 19-nov-2010 http://www.micron.com//products/pro ductdetails.html?product=products/dram _ modules/vlp _ rdimm//mt18vdvf12872y-4 ...

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